Deep Learning on Low Power Embedded Devices Using RISC-V Cores with an Extended Instruction SetVreča, Jure (Avtor) Brezočnik, Zmago (Mentor) Merchant, Farhad (Komentor) deep learningembedded systeminstruction setRISC-VThis thesis explores the possibility of running neural networks on microcontrollers and how to optimize their performance using instruction set extensions. Microcontrollers are seen as too weak to run neural networks. We challenge this view and show that stripped-down neural networks can run and be useful for some applications. We used an open-source microcontroller called PULPino to run our neural network. The benefit of various instructions and optimizations for minimizing energy consumption to run deep learning algorithms was evaluated. Hardware loops, loop unrolling, and the dot-product unit were implemented and tested. We developed an FPGA-based testing system to evaluate our hardware. We also developed a deep learning library and a test neural network for our hardware. We wrote two versions of the deep learning library. One version is the reference code, and the other is the optimized code that uses the dot product unit. Using the testing system, we tested the performance of the two versions. The synthesis was run to determine the power and energy consumption. We also tried out various optimizations to see if the performance could be improved. Using instruction set extensions and algorithmic optimizations we reduced the clock cycle count by 72% for the convolutional layers and by 78% for fully-connected layers. This reduced power consumption by 73%. We compare our results with related research.[J. Vreča]20202020-08-27 18:59:10Magistrsko delo/naloga77360sl