Methodology for test case generation based on sysml specificationsČučko, Tilen Antonio (Avtor) Truntič, Mitja (Mentor) Župerl, Uroš (Mentor) Novak, Ivan (Komentor) Engelbrecht, Martin (Komentor) Maletz, Michael (Komentor) systems engineeringverification and validationSysMLtest automatizationtest case creationIn the rapidly improving system design environment there is a need for automatization of tasks which are manual labor intensive. One of the core principles of systems engineering is verification and validation which is present iteratively throughout the development and on a higher system level at the end. For these verification and validation tasks test cases are used. The goal of this thesis is to extract the required test cases from the already present system models, mainly the test cases from function diagrams which are linear and cannot be extracted through state machine diagrams.[T. A. Čučko]20222022-11-24 17:35:47Magistrsko delo/naloga83430UDK: 681.5.015(043.2)COBISS_ID: 148615171sl