20.500.12556/DKUM-90737 Načrtovanje in verifikacija digitalnega bloka BiSS vmesnika Design and verification of the digital BiSS interface block Magistrsko delo obravnava izdelavo digitalnega BiSS (Angl. Bidirectional Serial Synchronous) bloka, ki ga je mogoče integrirati v podrejeno napravo. BiSS protokol je bil razvit z namenom učinkovite in zanesljive komunikacije na področju industrijske in senzorske komunikacije. Magistrsko delo prav tako predstavlja postopek načrtovanja digitalnega dela integriranih vezij. Ta zajema izdelavo RTL opis, sintezo, izdelavo položajnega načrta (Angl. Floorplan) ter verifikacijo. Končni blok je testiran do frekvence 10MHz vhodnega taktnega signala na MA liniji, med drugim pa zajema adaptivno časovno kontrolo (Angl. Ataptive Timeout), nastavljivo dolžino procesnih podatkov, dostopa do registrov preko kontrolne komunikacije ter delovanje v verižni vezavi (Angl. Daisy Chain). The master’s thesis addresses the design of a digital BiSS (Bidirectional Serial Synchronous) block that can be integrated into a slave device. The BiSS protocol was developed for effective and reliable communication in the fields of industrial and sensor communication. The thesis also presents the process of designing the digital part of integrated circuits. This involves creating RTL (Register Transfer Level) descriptions, synthesis, generating a floorplan, and verification. The final block is tested up to a frequency of 10MHz of the input clock signal on the MA line. Additionally, it includes adaptive timeout control, adjustable length of process data, access to registers via control communication, and operation in a daisy chain configuration. integrirano vezje digitalno vezje BiSS vmesnik integrated circuit digital circuit BiSS interface true true false [M. Ves] Slovenski jezik Angleški jezik Magistrsko delo/naloga 2024-09-18 15:37:55 2024-10-22 15:44:05 2025-01-29 13:06:42 0000-00-00 00:00:00 2024 0 Maribor 0 0000-00-00 NiDoloceno NiDoloceno NiDoloceno 0000-00-00 0000-00-00 0000-00-00 621.3.049.77(043.2) 224406019 MAG_Ves_Matevz_2024.pdf MAG_Ves_Matevz_2024.pdf 1 3DFAF17445737B0F04420F210CF6187C 4c7d11105a95beed06b8fb2349315d5a26df08f29fde470f9a3cd2a7b51b165d 727c5a2a-75c6-11ef-8939-00155d000105 https://dk.um.si/Dokument.php?lang=slv&id=185428 Fakulteta za elektrotehniko, računalništvo in informatiko 0 0 0