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DKUM
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Title:
PROGRAMSKO OKOLJE ZA NAČRTOVANJE PROGRAMIRLJIVIH VEZIJ S POMOČJO RAZVOJNE ENOTE
Authors:
ID
Zidarič, Blaž
(
Author
)
ID
Babič, Rudolf
(
Mentor
)
More about this mentor...
ID
Osebik, Davorin
(
Comentor
)
Files:
VS_Zidaric_Blaz_2009.pdf
(3,00 MB)
MD5: 35C2F58608E56C7E9093D111D34E6269
PID:
20.500.12556/dkum/f534db4e-7189-4625-a4ed-dd5ad5e71fb2
Language:
Slovenian
Work type:
Undergraduate thesis
Organization:
FERI - Faculty of Electrical Engineering and Computer Science
Abstract:
V diplomskem delu je opisano programsko okolje za načrtovanje programirljivih vezij s pomočjo razvojne enote. Predstavljen je postopek dela s programskim okoljem Xilinx ISE in simulatorjem ModelSim. Razvojna enota je namenjena predvsem pedagoškim namenom za povezavo med računalnikom ter programskim okoljem Xilinx ISE. Cilj diplomskega dela je bil pripraviti uporabniška navodila za delo s programskim okoljem za načrtovanje programirljivih vezij s pomočjo razvojne enote. Podan je tudi primer načrtovanja časovnega multiplekserja 2:1 s programirljivim vezjem Spartan 3E XC3S100E, ki je generiran s periodo 2 s.
Keywords:
razvojna enota
,
programsko okolje za načrtovanje Xilinx ISE
,
programirljiva vezja
,
uporabniška navodila
,
primer načrtovanja
Place of publishing:
Maribor
Publisher:
[B. Zidarič]
Year of publishing:
2009
PID:
20.500.12556/DKUM-10291
UDC:
004.4:621.38.049(043.2)
COBISS.SI-ID:
13308694
NUK URN:
URN:SI:UM:DK:5EABICLN
Publication date in DKUM:
18.05.2009
Views:
2872
Downloads:
207
Metadata:
Categories:
KTFMB - FERI
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Secondary language
Language:
English
Title:
SOFTWARE ENVIRONMENT FOR FPGA CIRCUIT DESIGN WITH DEVELOPTMENT UNIT
Abstract:
The diploma work thesis describes the software environment Xilinx ISE program surrounding for the planning field programmable gate array (FPGA) ming circuits design with a laboratory developing system. The designing with software environment Xilinx ISE and ModelSim is presented. he main part of the developing system is represented by the programmable programme circuits of the family XC3S100E by the firm Xilinx. The laboratory developing system is used mainly designed for education pedagogical purpose for within the FPGA circuits linked with a personal computer and the software environment Xilinx ISE interconection. The aim of the diploma work thesis was to prepare user instructions manual preparation. for the work with the programme surrounding, when planning programmable programming circuits for the laboratory developing system. The example of time multiplexer circuit design with Xilinx FPGA circuit XC3S100E is described.
Keywords:
development unit
,
software environment for planning Xilinx ISE
,
programmable circuits
,
user instruction
,
planning example
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