Akcijska logika dreves izvajanj z operatorjem unless : doktorska disertacija

Meolic, Robert

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Title:	Akcijska logika dreves izvajanj z operatorjem unless : doktorska disertacija
Authors:	ID Meolic, Robert (Author) ID Kapus, Tatjana (Mentor) More about this mentor...
Files:	phd-meolic-si.pdf (1,04 MB) MD5: 90186C455F6E94FE3128B7F64EB54A91 PID: 20.500.12556/dkum/94e6a967-06d9-4c47-99e9-ffa6005ac72f
Language:	Slovenian
Work type:	Not categorized
Typology:	2.08 - Doctoral Dissertation
Organization:	FERI - Faculty of Electrical Engineering and Computer Science
Abstract:	Doktorska disertacija definira in raziskuje akcijsko logiko dreves izvajanj z operatorjem unless (ACTLW). ACTLW je izjavna temporalna logika razvejanega časa. Izhaja iz logike ACTL, ki je bila vpeljana leta 1990 in je ena od uveljavljenih temporalnih logik za izražanje lastnosti modelov, ki temeljijo na dogodkih. ACTLW je fleksibilnejša od ACTL, saj ne vsiljuje uporabe notranjega dogodka T pri izražanju lastnosti. ACTLW je tudi nekoliko izraznejša od ACTL, saj vsebuje temporalni operator unless (W), katerega pomena v ACTL ni možno v celoti izraziti. Nasprotno pa lahko vse formule ACTL izrazimo z uporabo operatorjev ACTLW. ACTLW omogoča učinkovito izvedbo preverjanja modelov s podobnimi algoritmi kot pri preverjanju modela s CTL, kar je pomembna izboljšava glede na logiko ACTL. Doktorska disertacija podaja definicijo logike ACTLW, izpeljave vseh standardnih temporalnih operatorjev in algoritme za globalno preverjanje modela z ACTLW s simboličnim računanjem. Predstavljeni so tudi algoritmi za tvorjenje diagnostike pri ACTLW, za tvorjenje lineamih prič in protiprimerov pri ACTLW ter za tvorjenje avtomatov prič in proti primerov pri ACTLW. Doktorska disertacija je v celoto zaokrožena z vzorci formul ACTLW in dvema večjima praktičnima primeroma: verifikacijo več različnih algoritmov za medsebojno izključevanje in verifikacijo dveh asinhronih vezij za porazdeljeno medsebojno izključevanje.
Keywords:	formalne metode verifikacije sistemov, preverjanje modela, temporalna logika, doktorske disertacije, CTL, ACTL, ACTLW, diagnostika, problem medsebojnega izključevanja
PID:	20.500.12556/DKUM-67095
UDC:	004.23(043.3)
COBISS.SI-ID:	9981718
NUK URN:	URN:SI:UM:DK:OLOFPXQN
Publication date in DKUM:	04.08.2017
Views:	2153
Downloads:	145
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Categories:	Misc.
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Licences

License:	CC BY 4.0, Creative Commons Attribution 4.0 International

Link:	http://creativecommons.org/licenses/by/4.0/
Description:	This is the standard Creative Commons license that gives others maximum freedom to do what they want with the work as long as they credit the author.
Licensing start date:	02.08.2017

Secondary language

Language:	English
Title:	Action computation tree logic with unless operator
Abstract:	This thesis defines and studies action computation tree logic with unless operator (ACTLW). ACTLW is a propositional branching-time temporallogic. It is derived from logic ACTL, which was introduced in 1990 and which is one of established temporallogics for expressing properties of action-based models. ACTLW is more flexible than ACTL, because it does not impose the usage of silent action T in expressing of the properties. ACTLW has also a slightly greater expressive power than ACTL, because it contains temporal operator unless (W), whose meaning cannot be fully covered in ACTL. As opposite, all ACTL formulae can be expressed using ACTLW operators. ACTLW enables efficient implementation of model checking by using similar algorithms to those used for CTL model checking, which is a significant advantage in comparison to logic ACTL. The thesis gives a definition of logic ACTLW, derivations of all standard temporal operators, and algorithms for global ACTLW model checking using symbolic methods. Moreover, algorithms for generation of diagnostics for ACTLW, for generation of linear witnesses and counterexamples for ACTLW, and for generation of witness and counterexample automata for ACTLW are presented. The thesis is accomplished with patterns of ACTLW formulae and two larger practical examples: a verification of several different mutual-exclusion algorithms and a verification of two asynchronous distributed mutual-exclusion circuits.
Keywords:	formal methods of system verification, model checking, temporal logic, CTL, ACTL, ACTLW, diagnostics

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