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Title:
DSP SISTEM RAZŠIRJEN Z FPGA ZA VODENJE HITRO ODZIVNIH POGONOV
Authors:
ID
Čurkovič, Milan
(
Author
)
ID
Jezernik, Karel
(
Mentor
)
More about this mentor...
Files:
DR_Curkovic_Milan_2014.pdf
(5,84 MB)
MD5: DF7BFF4473D8E03A38A0567F04757335
Language:
Slovenian
Work type:
Dissertation
Typology:
2.08 - Doctoral Dissertation
Organization:
FERI - Faculty of Electrical Engineering and Computer Science
Abstract:
V delu je predstavljen razvoj in izdelava DSP sistema za vodenje motornih pogonov. Sistem je nato razširjen z zmogljivim FPGA vezjem za izvajanje časovno kritičnih procesov pri vodenju. Zmanjšanje zakasnitev in s tem razširitev frekvenčnega pasu nam pri tokovnem vodenju izboljša delovanje tudi pri nespremenljivi stikalni frekvenci pretvornika. Prikazana je izvedba vodenja položaja enosmernega motorja z aparaturno izvedbo tokovnega regulatorja. Kompenzacija nihanja navora BLDC motorja ob komutaciji je potrjena s simulacijo. V FPGA je izveden regulator faznih tokov PMSM motorja. Rezultati take izvedbe so potrjeni tako simulacijsko kot eksperimentalno in potrjujejo izboljšanje delovanja ob zmanjšanju nihanja navora ali zmanjšanju preklopnih izgub (manjše število preklopov) v primerjavi z drugimi metodami.
Keywords:
DSP
,
FPGA
,
FPGA izvedba
,
načrtovanje aparaturne opreme
,
nihanje navora
Place of publishing:
Maribor
Publisher:
[M. Čurkovič]
Year of publishing:
2013
PID:
20.500.12556/DKUM-43421
UDC:
681.5:621.313.2(043.3)
COBISS.SI-ID:
271692032
NUK URN:
URN:SI:UM:DK:SMXETNUM
Publication date in DKUM:
16.01.2014
Views:
3706
Downloads:
294
Metadata:
Categories:
KTFMB - FERI
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Secondary language
Language:
English
Title:
FPGA EXTENSION OF DSP SYSTEM FOR TIME-CRITICAL TASKS IN DRIVE CONTROL
Abstract:
This paper presents the development and implementation of DSP control system for motor drives. The system is then extended with a powerful FPGA circuit to implement time-critical processes in management. Reduced time delay and extended bandwidth improve performance even at a fixed converter switching frequency. Additional hardware current controller in DC motor position control loop is developed, simulated and experimentally tested. Compensation of BLDC motor torque ripple at commutation is confirmed by simulation. Within the FPGA is realized PMSM motor phase currents controller. The results of are verified by simulation and experimentally improve the operation by reduction of the switching losses (fewer inverter leg switching) in comparison by other methods.
Keywords:
DSP
,
FPGA
,
FPGA Implementation
,
Hardware design
,
Torque ripple
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